// **************************************************************
// COPYRIGHT(c)2016, Xidian University
// All rights reserved.
//
// IP LIB INDEX :  
// IP Name      :      
// File name    :  
// Module name  :  
// Full name    :  
// Time         : 2016 
// Author       : Wang-Weina 
// Email        : 327422289@qq.com
// Data         : 
// Version      : V 1.0 
// 
// Abstract     :
// Called by    :  
// 
// Modification history
// -----------------------------------------------------------------
// 
// 
//
// *****************************************************************

// *******************
// TIMESCALE
// ******************* 
`timescale 1ns/1ps 

// *******************
// INFORMATION
// *******************

//*******************
//DEFINE(s)
//*******************
//`define UDLY 1    //Unit delay, for non-blocking assignments in sequential logic

//*******************
//DEFINE MODULE PORT
//*******************
module LUT_5to1(
    input wire clk,
    input wire rst_n,
    input wire lookup_en,
    input wire[2:0] first_3,
    input wire[1:0] second_2,
    output reg match
    );

//*******************
//DEFINE LOCAL PARAMETER
//*******************
//parameter(s)

             
                                    

 

//*********************
//INNER SIGNAL DECLARATION
//*********************
//REGS
    
   
 

//WIRES
 

//*********************
//INSTANTCE MODULE
//*********************

 
 

//*********************
//MAIN CORE
//********************* 

always@(posedge clk or negedge rst_n)
  begin
    if(~rst_n)
      match <= 0;
    else if(lookup_en)
      match <=(first_3[2]&first_3[1]&first_3[0]) | (first_3[2]&second_2[1])|
              (first_3[1]&second_2[1]&second_2[0])|(first_3[0]&second_2[0]);
    else 
      match <= match;
  end

//*********************
endmodule    // hookup byte controller block
    